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SOT

Product and service

Product introduction
Small Outline Transistor is an abbreviation for Small Outline Transistor chip package. It is one of the surface mount packages. Generally, Small Outline transistors and integrated circuits have less than or equal to eight pins.

Product features
Compared to SOP, SOT is a smaller patch package for 8 pin or less devices.

Application
SOT is one of the most mature industry standard packages for Hall sensors, low voltage MOSFET tubes, power management chips, lithium electronic protection chips and other products.

Process characteristics
Refer to or meet JEDEC standards
Customized design lead frame design and multi-specification pad size to meet different customer needs
Green manufacturing, lead-free process

Reliability test standard
The test criteria is zero defects in 77 sampling units
JEDEC Prerequisite: J-STD-20/JESD22-A113
Temperature/humidity test: 85°C/85% RH, JEDEC 22-A101
Temperature/humidity test: 85°C/85% RH, JEDEC 22-A101
Temperature cycle test: -65~150 ℃, JEDEC22-A104
High temperature storage test: 150°C, JEDEC 22-A103
High acceleration stress test: 130°C/85% rh /33.5 PSIA, JEDEC 22-A110/A118

No.TypeLead countBody Lenth
(D)mm
Body Width
(E)mm
Body
Thickness
(A2)mm
Overall width
(E1)mm
Lead Pitch
mm
Lead
Width
( b)mm
Lead
Length
( L)mm
Standoff
(A1)mm
Max Downset
Size mil
Max Downset
Size um
LF Thickness
mm
LFPacking
1SOT23-3L(14R)3L2.92±0.11.60±0.11.10±0.12.80±0.20.950.33-0.500.35-0.600-0.1551×721300×25300.15214×48TAPE
2SOT23-3L(Flat PIN)3L2.92±0.11.60±0.11.10±0.13.95±0.050.950.33-0.5051×721300×25300.15214×48TAPE
3SOT23-5L(14R)5L2.92±0.11.60±0.11.10±0.12.80±0.20.950.33-0.500.35-0.600-0.1553×721350×18200.15214×48TAPE
4SOT23-5L(Flat PIN)5L2.92±0.11.60±0.11.10±0.13.95±0.050.950.33-0.5053×721350×18200.15214×48TAPE
5SOT23-6L(14R)6L2.92±0.11.60±0.11.10±0.12.80±0.20.950.33-0.500.35-0.600-0.1542×721066×18280.15214×48TAPE
6SOT23-6L(Flat PIN)6L2.92±0.11.60±0.11.10±0.13.95±0.050.950.33-0.5042×721066×18280.15214×48TAPE
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